vlsi digital-design

Modified MIPS Processor (Cadence)

VLSI lab project implementing a simplified 32-bit MIPS-style processor with a limited instruction set in Cadence.

ML
Mehedi Hossen Limon
Engineer · Talibul Ilm · Writer
· 1 min read · 64 words

Overview

VLSI laboratory sessional project: implementation of a 32-bit simplified MIPS-style processor supporting a limited instruction set (thirteen instructions) using Cadence tools.

Learning outcomes

  • Digital system design and computer architecture basics
  • Translating an ISA subset into hardware structure
  • Tool flow exposure in a university VLSI setting

Note

Academic lab implementation—not a production CPU design. No public repository is listed for this project on GitHub.